Burst Mode Clock and Data Recovery Circuit and Method

ABSTRACT

Burst mode clock and data recovery (BCDR) circuit and method capable of fast data recovery of passive optical network (PON) traffic. An over-sampled data stream is generated from an input burst data signal and a phase interpolator generates sampling clock signals using a reference clock and phase information. A phase estimation unit (PEU) determines a phase error in the over-sampled data streams; and a phase retrieval unit sets the phase interpolator with the respective phase information of the input burst data signal prior to reception of the input burst data signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 11/604,748, filed Nov. 28, 2006, which will issue as U.S. Pat. No. 8,243,869 on Aug. 14, 2012, which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to passive optical networks (PONs) and, more particularly, to BCDR circuits for enhancing the efficiency of data reception in PONs.

2. Background Art

Many communication networks that provide high bit-rate transport over a shared medium are characterized by non-continuous or burst mode data transmission. An example for such network is a passive optical network (PON) 100 schematically shown in FIG. 1. A typical PON 100 includes a plurality of optical network units ONUs 120-1 through 120-M coupled to an OLT 130 via a passive optical splitter 140. Since all ONUs function in like manner, they will be collectively referred to by the reference numeral 120 in the following description unless reference is made to a specific ONU. Traffic data transmission may be achieved using GEM fragments or ATM cells over two optical wavelengths, one for the downstream direction and another for the upstream direction. Thus, downstream transmission from the OLT 130 is broadcast to all the ONUs 120. Each ONU 120 filters its respective data according to, for example, pre-assigned labels.

The OLT 130 continuously transmits downstream data to the ONUs 120 and receives upstream burst data sent to OLT 130 from ONUs 120. The OLT 130 broadcasts data to the ONUs 120 along a common channel so that all the ONUs 120 receive the same data. An ONU 120 transmits data to the OLT 130 during different time slots allocated by the OLT 130. That is, the OLT 130 is aware of the exact arrival time of data and the identity of a transmitting ONU 120.

A receiver in the OLT 130 uses a burst mode clock and data recovery (BCDR) circuit to generate a clock corresponding to the incoming data, thereby correctly retiming the incoming data. In the case of burst data transmission, a preamble is transmitted before the data to obtain the clock information before sampling the data.

Conventional clock and data recovery (CDR) and BCDR circuits are typically based on a phase locked loop (PLL) or over-sampling techniques. Examples of PLL based CDR and BCDR circuits may be found in U.S. Pat. Nos. 5,757,872, 5,237,290 and 6,259,326 as well as in US patent publications US2005281366 (Shachar et al.), US2006115035 (Yu et al.) and US2006031701 (Nam et al.) all of which are incorporated herein by reference for their useful background information.

In over-sampling based CDR and BCDR techniques, in general, data is obtained by sampling data over a multiphase clock. FIG. 2 shows a schematic block diagram of a typical over-sampling based BCDR circuit 200. The BCDR circuit 200 includes a reference oscillator 210 and a phase interpolator 220 that are used together to provide a number N of clock signals at the oscillating frequency generated by the oscillator 210. Each such clock signal is shifted in phase by a factor 1/N of the clock cycle with respect to the preceding signal. The clock signals are input into an over-sampler 230 utilized to retime the data and clock. The over-sampler 230 receives an input data signal and, using the clock signals, generates a digital representation of at least one complete period of the input data signal. A phase estimation circuit (PEC) 240 receives this digital representation and uses that representation to generate an estimate of the phase of the input data signal, as received. This estimate is input into the phase interpolator 220 to generate a correct sampling clock signal (e.g., the clock signal having a sampling edge closest to the middle of the bit-interval of input data signal) for future sampling of the input data signal. The PEC 240 also produces frequency information to align the recovered clock with the transmitted clock. Examples of over-sampling based CDR circuits may be found in U.S. Ser. No. 10/460,572 and in U.S. Pat. Nos. 6,122,335, 6,259,326 and 6,269,137, which are incorporated herein by reference for their useful background information. The over-sampling based CDR circuits are capable of both fast locking to a rapidly changed phase of the transmission clock and stable tracking of a slowly changing phase.

BRIEF SUMMARY OF THE INVENTION

According to a first aspect of the invention, there is provided a burst mode clock and data recovery (BCDR) circuit capable of fast data recovery of passive optical network (PON) traffic, the BCDR circuit comprising:

an over-sampler capable of over sampling an input burst data signal and being further capable of generating over-sampled data streams;

a phase interpolator capable of generating sampling clock signals using a reference clock and phase information;

a phase estimation unit (PEU) capable of determining a phase error in the over-sampled data streams; and

a phase retrieval unit capable of setting the phase interpolator with the respective phase information of the input burst data signal prior to reception of the input burst data signal.

According to a second aspect of the invention, there is provided a method for fast recovery of burst data transmitted from an optical line unit (ONU) to an optical line terminal (OLT) in a passive optical network (PON), the method comprising:

prior to receiving of an input burst data signal sent from the ONU, retrieving phase information associated with ONU;

generating sampling clock signals using a reference clock and the retrieved phase information; and

over-sampling the input burst data signal using sampling clock signals to generate over-sampled data streams.

According to a third aspect of the invention, there is provided a burst mode clock and data recovery (BCDR) circuit capable of fast data recovery of passive optical network (PON) traffic, the BCDR circuit comprising:

an over-sampler capable of over sampling an input burst data signal and being further capable of generating over-sampled data streams;

a phase interpolator capable of generating sampling clock signals using a reference clock and an input sampling point;

a phase estimation unit (PEU) capable of directly estimating an exact sampling point for the input burst data signal; and

a phase mover capable of adjusting the phase interpolator to the exact sampling point.

According to a fourth aspect of the invention, there is provided a method for fast recovery of burst data transmitted from an optical line unit (ONU) to an optical line terminal (OLT) in a passive optical network (PON), the method comprising:

receiving an input burst data signal;

estimating an exact sampling point for the input burst data signal;

adjusting a phase interpolator to generate sampling clock signals at the exact sampling point; and

over-sampling the input burst data signal using sampling clock signals to generate over-sampled data streams.

According to a fifth aspect of the invention, there is provided a method for converting a conventional clock and data recovery (CDR) circuit into a burst mode CDR (BCDR), the method comprising:

providing a conventional CDR circuit that includes at least a digital filter for performing frequency correction functions performed by the digital filter; and

disabling output signals of the digital filter that includes frequency information.

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

In order to understand the invention and to see how it may be carried out in practice, a preferred embodiment will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

FIG. 1 is a schematic block diagram of a prior art PON;

FIG. 2 is a schematic block diagram of a typical prior art over-sampling based CDR circuit;

FIG. 3 is a block diagram of a BCDR circuit disclosed in accordance with one embodiment of the present invention; and

FIG. 4 is a block diagram of a BCDR circuit disclosed in accordance with another embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3 is a block diagram of a burst mode clock and data recovery (BCDR) circuit 300 implemented in accordance with one non-limiting embodiment of the present invention. The BCDR circuit 300 includes an over-sampler 310, a phase interpolator 320, a phase estimation unit (PEU) 330, a digital filter 340, a phase retrieval unit 350, and a pipeline 360. In one embodiment, the BCDR circuit 300 is installed in an OLT (e.g., OLT 130) and adapted to receive burst data sent from ONUs (e.g., ONUs 120) over the common channel.

The BCDR circuit 300 is based on a phase retrieval technique that allows for the immediate lock onto the phase of an input data signal, thereby recovering the data without delay and with a high level of accuracy. In a PON system, an OLT, in general, knows the exact time that an ONU transmits data and its identity (ID number) as the OLT allocates the time slots for transmissions. In addition, the common channel (i.e., optical fiber) has a maximum allowed change in the group-delay. The phase retrieval technique takes advantage of these attributes to set the phase of a clock signal used to recover data sent from an ONU prior to receiving data from that ONU.

The BCDR circuit 300 acquires the phase information on each ONU during setup mode and updates this information during the normal mode of operation. The phase information is saved in a memory 352 of the phase retrieval unit 350. The memory 352 is a read/write programmable memory. The phase retrieval unit 350 further includes a phase selector 354 that selects the source of the phase information to be provided to the phase interpolator 320. In a normal mode of operation the source is the memory 352 and in a set-up mode the source is the digital filter 340.

During the normal mode of operation of a PON, the BCDR circuit 300 is informed, by a Burst Reset 306 signal, of an ONU that is expected to send data. Using the ID of that ONU, its respective phase information is retrieved from the memory 352 and input to the phase interpolator 320. The phase interpolator 320 is used to generate a number N of sampling clock signals 301 at the oscillating frequency provided by a reference clock 302. Each signal 301 is shifted in phase by a factor 1/N of the clock cycle with respect to the preceding signal plus the retrieved phase. The over-sampler 310 receives input burst data signal 303. Using the sampling clock signals 301, it generates a number M of digital sampled data streams 304. The number M equals to the number of samples of a unit interval of data, i.e., the over-sampler 310 performs over sampling by a factor equal to M.

The PEU 330 receives the M data streams 304 and extracts the phase information of the input data signal 301. Specifically, the PEU 330 calculates the sampling point of data and the phase error.

The digital filter 340 compares the extracted phase information to the phase of the respective current transmitting ONU as stored in the memory 352. If the comparison results in inequality, the extracted phase information is saved in the memory 352 and sent to the phase interpolator 320 for future sampling of the input data signal 301 to recover the data in that signal; otherwise, data is sampled using the previous generated sampling signals.

The sampled data streams 304 are also input to the pipeline 360 in order to enable the selection of a correct data stream without losing data. The sampled data streams 304 propagate through the pipeline 360 and at its output a single stream is selected. That is, a data stream that results from sampling by what was determined to be the most accurate sampling clock signal 301 is selected by the digital filter 340. The selected data stream may also be saved in the memory 352. In addition, a first-in-first-out (FIFO) data structure 365 is coupled to the pipeline 360 to prevent the loss of data that could result from the potential lack of synchronization between the local ONU clock and the reference clock 302.

As mentioned above the acquisition of the phase information for each ONU is performed during the set-up mode of operation, which takes place during the activation procedures of an ONU. Two states are possible during this mode: serial number and ranging. In the serial number state, the OLT tries to detect the serial number that is the ONU's identifier (ID), while in the ranging state the OLT tries to determine the range between the terminal units (i.e., ONUs and OLT). Regardless of the active state, in the set-up mode the exact arrival time of data bursts sent from a designated ONU is unknown. However, this time is expected to occur at a predefined window (“ranging window”). With that said, determining the beginning of a ranging window using a BCDR circuit is one of the difficulties of OLT systems. For this purpose, the BCDR circuit 300 includes a burst detector 370 as further discussed below.

The burst detector 370 detects, with high accuracy, an incoming burst data during the set-up mode. A burst data is received in a form of a cell, which includes a preamble and data portions. The preamble has a predefined pattern of bits (e.g., [0101010101]) and its length is greater than ‘m’ bytes (m>2). The burst detector 370 processes sampled data streams 304 and tries to detect two types of events: a) a preamble pattern, and b) number of transitions. The burst detector 370 searches for a preamble pattern in each of the data streams. If a pattern is detected in any of the streams and within a predefined limit of length, then a preamble detected signal is asserted. The burst detector 370 further counts the number of transitions from ‘1’ to ‘0’ and from ‘0’ to ‘1’ in all sampling streams 304 during a predefined time interval. If the total count is within a predefined threshold a burst detection signal is asserted. The burst detector 370 can further assert a detection signal based on any combination of the two detection signals. The incoming burst indication is input to the pipeline 360, enabling the output of a selected stream only once a burst is detected, and thereby preventing the output of noise.

The incoming burst indication is further input to the digital filter 340 indicating when to begin the acquisition of phase information of an ONU. To this end, the phase interpolator 320 generates a number N of clock signals 301 at the oscillating frequency provided by a reference clock 302. Each clock signal 301 is shifted in phase by a factor 1/N of the clock cycle plus an arbitrary phase value with respect to the preceding signal. In one embodiment the initial phase can be selected and dithered to achieve fast detection of an ONU. The over-sampler 310 receives an input data signal 303 sent during the ranging window and, using the clock signals 301, generates digital sampled data streams 304. The PEU 330 receives the streams 304 and determines whether the sampled streams include a phase error.

If so, the digital filter 340 instructs the phase interpolator 320 to shift the clock signals 301 by b/k, where b represents the number of phase errors detected by the PEU 330 at the sampling point and k is the maximum number of possible phase error that can be detected in a single clock cycle. Each clock signal 301 is now shifted in phase by a factor b/k of the clock cycle plus the arbitrary phase value with respect to the preceding signal, i.e., the j^(th) clock signal is:

${{clock}(j)} = {{clk\_ ref}{\left( {a + \frac{j}{N} + \frac{b}{k}} \right).}}$

The parameter α is an arbitrary phase determined at the beginning of the process and j is an integer number equals to 0, . . . , or N−1.

Subsequent sampled data streams 304 generated by the over sampler 310 using the new clock signals include no phase error. Subsequent sampled data streams 304 generated by the over sampler 310 using the new sampling clock signals 301 will continue to follow and correct the errors as detected by the PEU. The digital filter 340 saves the phase information of the clock signal 301 in the memory 352 in an entry of the respective ONU. It should be noted that during the set-mode, phase correction is optional where a single stream without making any phase correction. In an embodiment of the present invention the BCDR circuit 300 may recover incoming burst data where only a single sampled data stream is fed from the over-sampler 310 to the output of circuit 300. In this embodiment the BCDR circuit 300 may function without the pipeline 360, FIFO 365, and burst detector 370. In addition the action of selecting a sampled data stream, as preformed by the digital filter 340, is not required.

FIG. 4 shows a non-limiting block diagram of a BCDR circuit 400 implemented in accordance with another embodiment of the present invention. The BCDR circuit 400 includes an over-sampler 410, a phase interpolator 420, a phase estimation unit (PEU) 430, a digital filter 440, and a phase mover 450. The BCDR circuit 400 also includes a pipeline 460 coupled to the output of the over-sampler 410 and a burst detector 470 coupled to the digital filter 440. Both the pipeline 460 and burst detector 470 have the same functionality described in greater detail above. In one embodiment, the BCDR circuit 400 is installed in an OLT (e.g., OLT 130) and adapted to receive burst data sent from ONUs (e.g., ONUs 120) over the common channel.

The BCDR circuit 400 is based on a phase movement technique that allows accelerating the recovery of received data. As discussed in the background of the invention, techniques have been proposed that use the sampled signals to estimate the correct phase of a clock signal to recover the data. This phase estimation is fed into the phase interpolator 420, and thereby allows the phase interpolator 420 to generate sampling clock signals with a correct phase. Typically, this is performed by: a) changing the phase (or sampling point) within the phase interpolator 420 in a predefined interval; b) generating new sampled data signals; c) estimating the phase error; and, d) changing again the sampling point in a predefined interval. The process is repeated until locking on the correct phase and is referred to as “phase movement”.

The present invention accelerates the phase movement process by implementing and integrating the digital filter 440 and phase mover 450 in the BCDR circuit 400. Specifically, the digital filter 440 is configured with the physical parameters of the phase interpolator 420. The parameters include at least the maximal allowed phase change at each move and the minimum waiting time between moves. To recover the data from an input burst data signal 403 during the normal mode of operation, the phase interpolator 420 generates a number N of clock signals 401 at the frequency provided by a reference clock 402. Each signal 401 is shifted in a phase by a factor 1/N of the clock cycle with respect to the preceding signal. The over-sampler 410 receives the input data signal 403 and using the clock signals 401 generates digital sampled data streams 404.

The PEU 430 extracts from the sampled data streams 404 the phase (i.e., the sampling point) required to recover the data. The sampling point is input to the digital filter 440. The digital filter 440 knows the current state of the phase interpolator 420 and determines a new state to which the phase interpolator 420 should be transferred in order to generate the correct sampling clock signals 401. The phase mover 450 moves the phase interpolator 420 to its new state under the control of the digital filter 440, which takes into account the physical parameters of the phase interpolator 420. This allows adjusting the phase interpolator 420 to the correct sampling point with a minimal delay. While adjusting the phase interpolator 420 to its new state, the digital filter 440 can be configured either to disregard or to process phase estimations provided by the PEU 430. Specifically, when the phase error measured by the PEU 430 is above a predefined threshold, then the phase estimations are ignored, and thus sampled data streams generated during the phase adjustment do not affect the phase interpolator 420. Otherwise, the estimations are processed by the digital filter 430. Typically, once the phase interpolator 420 is set to its new state, the digital filter 440 tracks changes in the phase and enables small movement of the phase interpolator 420.

During set-up mode, the digital filter 430 sets the phase interpolator 420 to a state representing a correct sampling point using the same process described herein. However, the process for setting the phase interpolator 420 begins only upon assertion of the incoming burst indication by the burst detector 470. Until such indication is asserted the digital filter 440 can use generated sampled streams to determine the new state of the phase interpolator 420.

In an embodiment of the present invention the BCDR circuit 400 may recover incoming burst data where only a single sampled data stream is fed from the over-sampler 410 to the output of circuit 400. In this embodiment the BCDR circuit 400 may function without the pipeline 460, FIFO 465, and burst detector 470. In addition the action of selecting a sampled data stream, as preformed by the digital filter 440, is not required.

It should be noted that in PONs the clocks of the transmitting ONU and receiving OLT are synchronized. Therefore, there is no need to recover the frequency factor of the clock from a received input signal, as its value is known. Based on this description and facts, the present invention discloses a technique for modifying conventional and commercial CDR circuits into a burst mode CDR circuit applicable to many different systems, such as PON systems or others. This is performed by disabling signals including frequency information and frequency correction functions typically performed by the digital filter. This information is utilized to synchronize the clocks, i.e., allowing the receiver and transmitter clock to operate at exactly the same frequency. 

1. A burst mode clock and data recovery (BCDR) circuit, comprising: an over-sampler configured to oversample a burst data signal according to a plurality of sampling clock signals to provide a plurality of over-sampled data streams; a phase interpolator configured to generate the plurality of sampling clock signals, the plurality of sampling clock signals being phase shifted utilizing a phase information corresponding to an estimated phase of the burst data signal; a phase retrieval unit configured to provide the phase information prior to the oversampler oversampling the burst data signal; and a pipeline configured to output a recovered data signal based on an accuracy of the plurality of sampling clock signals.
 2. The BCDR circuit of claim 1, further comprising: a reference clock module configured to provide a reference clock signal, wherein the phase interpolator is further configured to phase shift the plurality of sampling clock signals by a factor proportional to the reference clock signal plus a phase represented by the phase information.
 3. The BCDR circuit of claim 2, wherein the factor is a reciprocal of a number of the plurality of sampling clock signals generated by the phase interpolator.
 4. The BCDR of claim 1, further comprising: a digital filter configured to extract and to compare a phase from an over-sampled data stream from among the plurality of over-sampled data streams to a reference phase to determine the accuracy of the phase of the plurality of sampling clock signals.
 5. The BCDR circuit of claim 1, wherein the phase retrieval unit further comprises: a phase selector configured to select a source of the phase information; and a memory configured to store the phase information.
 6. The BCDR circuit of claim 5, wherein the phase selector is further configured to select the source of the phase information from among the phase information stored in the memory or an extracted phase information determined from the plurality of over-sampled data streams.
 7. The BCDR circuit of claim 6, wherein the burst data signal is received from an optical network unit (ONU), wherein the BCDR circuit is configured to operate in a setup mode of operation during an activation procedure of the ONU, and wherein the phase selector unit is further configured to select the source of the phase information as the extracted phase information during the setup mode of operation.
 8. The BCDR circuit of claim 7, wherein the BCDR circuit is further configured to operate in a normal mode of operation after the activation procedure, and wherein the phase selector unit is further configured to select the phase information stored in the memory during the normal mode of operation.
 9. The BCDR circuit of claim 1, further comprising: phase estimation unit (PEU) configured to determine the accuracy of the plurality of sampling clock signals by comparing the estimated phase to a phase threshold.
 10. The BCDR circuit of claim 1, further comprising: a burst detector configured to control the pipeline in response to the detection of the burst data signal.
 11. A burst mode clock and data recovery (BCDR) circuit, comprising: an over-sampler configured to oversample a burst data signal according to a plurality of sampling clock signals to provide a plurality of over-sampled data streams; a phase estimation unit (PEU) configured to provide a plurality of phase estimates corresponding to phases of the plurality of over-sampled data streams; a digital filter configured to process the plurality of over-sampled data streams when a phase estimate from among the plurality of phase estimates is below a phase error threshold; a phase mover configured to receive phase information from the digital filter and to provide a phase mover signal based on the phase information; and a phase interpolator configured to generate clock signals having substantially the same phase as the burst data signal based on the phase mover signal.
 12. The BCDR circuit of claim 11, wherein the BCDR circuit is coupled to an optical line terminal (OLT) device.
 13. The BCDR circuit of claim 11, wherein the PEU is further configured to compare the phase of the plurality of phase estimates to a threshold phase to determine a plurality of phase errors.
 14. The BCDR circuit of claim 11, wherein the digital filter is further configured to disregard an over-sampled data stream from among the plurality of over-sampled data streams when a phase estimate from among the plurality of phase estimates is above the phase error threshold.
 15. The BCDR circuit of claim 11, wherein the phase mover is further configured to provide the phase mover signal based on a physical parameter of the phase interpolator.
 16. In an optical line terminal (OLT), a method comprising: receiving a plurality of data signals from an optical network unit (ONU); sampling the plurality of data signals according to a plurality of sampling clock signals to provide a plurality of data streams; and selecting a data stream from among the plurality of data streams corresponding to an accuracy of a phase of a sampling clock signal from among the plurality of sampling clock signals.
 17. The method of claim 16, further comprising: determining a phase error of a data stream from among the plurality of data streams, and wherein the step of generating comprises: generating a sampling clock signal from among the plurality of sampling clock signals based on the phase error.
 18. The method of claim 17, wherein the step of selecting comprises: selecting the data stream from among the plurality of data streams when the phase error is below a phase error threshold.
 19. The method of claim 17, further comprising: calculating a sampling point based on a phase of a data stream from among the plurality of data streams, and wherein the step of generating comprises: generating the sampling clock signal utilizing the sampling point and the phase error.
 20. The method of claim 19, further comprising: repeating the steps of calculating the sampling point through generating the sampling clock signal for the plurality of data streams. 